1. Field of the Invention
The present invention relates to the field of semiconductor devices, more particularly to the field of P-channel semiconductor devices. The present invention relates to enhancing reliability, more particularly negative bias temperature instability (NBTI) reliability, of such devices. Embodiments of the present invention are particularly useful for sub-1 nm EOT devices.
2. Description of the Related Technology
NBTI is a significant reliability concern for submicron CMOS technologies, particularly to the PMOS transistors therein. It is widely believed that NBTI degradation is due to generation of interface traps, which are unsaturated silicon dangling bonds. One of the most popular models explaining NBTI phenomenon is the reaction diffusion model. This model proposes that the generation of interface traps is because of a hole induced electrochemical reaction at the Si—SiO2 interface. In the initial times the degradation is reaction rate controlled, however, with time the phenomenon becomes diffusion limited. In addition to this, it is also believed that a consistent part of the NBTI degradation is due to a hole-trapping mechanism, whereby a hole gets trapped in a trap state, causing a shift in the threshold voltage.
NBTI has always been associated with the CMOS development, but it was not considered of great importance because of the low electric fields in operation. However, as there is an increasing demand for higher drive current, NBTI has become a major reliability problem for the semiconductor industry, in particular it is a key reliability issue in MOSFETs.
When a P-channel semiconductor device, such as a PMOSFET, is biased with negative gate voltages especially at elevated temperatures, i.e. normal operating conditions, degradation of main device parameters (threshold voltage, transconductance, drive current, subthreshold slope, etc.) is observed: NBTI manifests as an increase in the threshold voltage and a consequent decrease in drain current and transconductance. The mechanism is caused by holes interacting with defect precursors in the oxide and at the oxide/semiconductor interface.
Also the reduction of effective oxide thickness (EOT), which is one of the most efficient ways to improve MOSFET performance, enhances NBTI reliability problems due to increased oxide electric field (Eox). For sub-1 nm EOT Si PFETs, 10 year lifetime can be guaranteed only at gate voltages much lower than the expected operating voltages (e.g., expected operating voltage VDD=1 V; |VG−Vth|=0.7 V for a |Vth|=0.3 V).
As such, what is desired is a system and method that can alleviate NBTI in P-channel semiconductor devices while improving circuit performance.